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AES Key Wrap cores

Overview

The Helion AES Key Wrap Cores implement the AES-based Wrap and Unwrap algorithms specified in NIST SP 800-38F. They also support the AESKW algorithm specified in the ASC ANS X9.102-2008 standard for wrapping keys and associated data. They are intended for protecting cryptographic key material within applications where key data must be transmitted over insecure communication networks, or stored within an untrusted environment.

Helion AES Key Wrap Solutions

The Helion AES Key Wrap and Unwrap cores take as input the key material to be wrapped or unwrapped, along with a Key Encryption Key (KEK). Both cores support all KEK sizes (128, 192 and 256 bits) specified by both the SP 800-38F and X9.102-2008 key wrap standards. The Unwrap core automatically performs authentication of the unwrapped key material and flags success or failure of the operation.

Measured Area and Performance
The table below shows typical resource requirements for the Key Wrap and Unwrap core versions with support for all KEK sizes (128, 192, and 256-bit) in different target technologies. The minimum times shown are for the wrapping and unwrapping of 256 bits of key material using a 256-bit KEK at the core's maximum clock rate.

TARGET KEY WRAP
AREA
KEY WRAP
MIN TIME
KEY UNWRAP
AREA
KEY UNWRAP
MIN TIME
Altera
Cyclone III/IV (C6)
710 LEs
3 M9Ks
114 us 804 LEs
3 M9Ks
128 us
Altera
Cyclone V (C6)
367 ALMs
2 M10Ks
79 us 412 ALMs
2 M10Ks
92 us
Altera
Arria II GX (C4)
371 ALMs
3 M9Ks
75 us 425 ALMs
3 M9Ks
75 us
Altera
Arria V GX (C4)
364 ALMs
2 M10Ks
76 us 387 ALMs
2 M10Ks
82 us
Altera
Arria 10 (E2L)
321 ALMs
2 M20Ks
53 us 358 ALMs
2 M20Ks
62 us
Altera
Stratix IV (C2)
363 ALMs
3 M9Ks
56 us 428 ALMs
3 M9Ks
57 us
Altera
Stratix V (C1)
390 ALMs
2 M20Ks
50 us 432 ALMs
2 M20Ks
50 us
Microsemi
ProASIC3 (-2)
1313 Tiles
3 RAMs
166 us 1542 Tiles
3 RAMs
203 us
Xilinx
Spartan-3A (-5)
260 slices
2 RAMB16s
139 us 302 slices
2 RAMB16s
148 us
Xilinx
Virtex-5 (-3)
119 slices
1 RAMB16
56 us 135 slices
1 RAMB16
61 us
Xilinx
Spartan-6 (-3)
115 slices
1 RAMB16
82 us 128 slices
1 RAMB16
77 us
Xilinx
Virtex-6 (-3)
113 slices
1 RAMB18
51 us 126 slices
1 RAMB18
56 us
Xilinx
Artix-7 (-3)
117 slices
1 RAMB18
62 us 129 slices
1 RAMB18
68 us
Xilinx
Kintex-7 (-3)
116 slices
1 RAMB18
47 us 131 slices
1 RAMB18
51 us
Xilinx
Virtex-7 (-3)
116 slices
1 RAMB18
47 us 131 slices
1 RAMB18
51 us
Datasheets

For full details of the Helion AES Key Wrap IP core family please download the datasheet for your target technology. Please note that in Xilinx FPGA only, the cores are also available as a Standard version, so there are separate Key Wrap and Key Unwrap core datasheets.

Click here for the Microsemi (Actel) FPGA core data sheet (PDF format)
Click here for the Xilinx FPGA Key Wrap core data sheet (PDF format)
Click here for the Xilinx FPGA Key Unwrap core data sheet (PDF format)
Click here for the Altera FPGA core data sheet (PDF format)

Contact

For more detailed information on this or any of our other products and services, please feel free to email us at helioncores@heliontech.com and we will be pleased to discuss how we can assist with your individual requirements.


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