Overview
The ever-increasing demands of network traffic make compression a necessity, to increase
apparent bandwidth and reduce congestion, especially on wireless networks such as cellular
microwave backhaul, or WiMAX (802.16).
Some data, such as audio and video, is already compressed, but there is plenty of redundancy
in the remainder, both in the protocol headers and in the payload.
Algorithms such as Robust Header Compression (RoHC) are used to reduce the header overhead,
but the payload redundancy is best removed using a general purpose compression algorithm
such as LZRW, which can be optimised for network frame-sized data chunks.
Helion Payload Compression Solutions
Helion's Compression System utilises one or more of Helion's proven LZRW Compression Cores.
The throughput scales almost linearly from 1 to 5 engines, covering a range of 500Mbps-5Gbps
with current ASIC and FPGA technologies (depending upon clock speed). The system can be
configured for either standard frames (up to ~2K bytes), or jumbo frames (up to ~9K or even ~16K bytes).
It is designed for easy in-line operation with network packets, yet is protocol agnostic.
A generic but flexible header pass-thru allows different protocol and encapsulation scenarios.
The final re-encapsulation decision is left to the user, either by changing existing protocol
type fields or setting flags in proprietary link-layer headers.
The system contains all the logic needed to queue and allocate packets fairly across
multiple engines, and to ensure the original order is preserved at the output. Latency
is broadly equivalent to the store and forward time, since the whole packet must be seen
to make a decision whether compression has succeeded or not.
The Compression System is supported by a testbench which allows arbitrary PCAP
format packet captures of real network data to be simulated, to investigate
compression performance, and measure throughput and latency.
These high performance cores are available in versions for use in ASIC, Altera,
Lattice and Xilinx FPGA, and in common with all Helion IP cores they
have been designed with each technology firmly in mind to yield the very
best and most efficient results.
Measured Area and Performance
Example figures for 2-engine system with 2K max frame size using LZRW1,
showing total of separate Compress and Expand sub-systems.
TARGET |
THROUGHPUT1 |
AREA2 |
RAM2 |
ASIC (65nm CMOS) |
2.6 Gbps |
<60k gates |
304 Kbits RAM |
Altera Cyclone IV (C6) |
1.6 Gbps |
7000 LEs |
46 M9Ks |
Altera Cyclone V (C6) |
2.0 Gbps |
TBC ALMs |
38 M10Ks |
Altera Arria II GX (C4) |
2.8 Gbps |
TBC ALMs |
46 M9Ks |
Altera Arria II GZ (C3) |
2.6 Gbps |
TBC ALMs |
46 M9Ks |
Altera Arria V GX (C4) |
2.2 Gbps |
TBC ALMs |
38 M10Ks |
Altera Arria V GZ (C3) |
2.8 Gbps |
TBC ALMs |
22 M20Ks |
Altera Stratix IV (C2) |
2.8 Gbps |
TBC ALMs |
46 M9Ks |
Altera Stratix V (C2) |
3.4 Gbps |
TBC ALMs |
22 M20Ks |
Lattice ECP3 (-8) |
1.4 Gbps |
4200 slices |
22 EBRs |
Xilinx Spartan-3A (-5) |
1.2 Gbps |
3700 slices |
22 RAMB16s |
Xilinx Spartan-6 (-2) |
1.6 Gbps |
1300 slices |
19 RAMB16s |
Xilinx Artix-7 (-2) |
2.0 Gbps |
TBC slices |
22 RAMB18s |
Xilinx Virtex-5 (-3) |
2.6 Gbps |
TBC slices |
22 RAMB18s |
Xilinx Virtex-6 (-3) |
2.6 Gbps |
TBC slices |
22 RAMB18s |
Xilinx Virtex-7 (-2) |
2.6 Gbps |
TBC slices |
22 RAMB18s |
Xilinx Kintex-7 (-2) |
2.6 Gbps |
TBC slices |
22 RAMB18s |
1. Throughput figures are per link direction and are typical for the uncompressed
interface. They are also slightly data dependant.
2. For jumbo frame support (9K max frame), area increases slightly and RAM increases
significantly (see datasheet for details).
Datasheets
For full details of the Helion Compression System, including detailed performance figures
for throughput, frame rates, latency, and compression ratio, please contact Helion.
Contact
For more detailed information on this or any of our other products and services,
please feel free to email us at
helioncores@heliontech.com and we will be pleased to discuss how we can assist
with your individual requirements.
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