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LZRW Compression cores

Overview

Data compression is important in any application where storage or network capacity is limited. Lossless compression allows complete recovery of the original data, so is ideally suited to these applications. Previously compression was often handled in software, but today's requirements mean that high performance hardware acceleration of the compression processing is becoming a basic requirement. The LZRW family of algorithms provide general-purpose lossless compression with good performance at high throughputs and low memory utilisation. The Helion LZRW Compression core is therefore a basic building block for many applications.

Helion LZRW Solutions

Helion's LZRW core is a high performance hardware implementation of either LZRW1-A or LZRW3. LZRW1 is chosen for short history depths, as it allows a much smaller and faster expander, whereas LZRW3 allows better compression using longer history depths. There is further information on the algorithms on the Compression Backgrounder page.

A choice of separate compression and expansion engines, or a combined compressor / expander is available, each capable of processing at gigabit rates in typical ASIC or FPGA targets. These high performance cores are available in versions for use in ASIC, Altera, Lattice and Xilinx FPGA, and in common with all Helion IP cores they have been designed with each technology firmly in mind to yield the very best and most efficient results.

Measured Area and Performance

Example figures for combined LZRW1 Compressor/Expander. The functions are available separately, as smaller cores. The LZRW1 Expander is considerably smaller and uses much less memory.

TARGET THROUGHPUT1,2 AREA2 RAM3
ASIC (65nm CMOS) 1.3 Gbps <15k gates 64 to 580 Kbits RAM
Altera Cyclone IV (C6) 800 Mbps 1669 LEs 12 to 19 M9Ks
Altera Cyclone V (C6) 1.0 Gbps 710 ALMs 8 to 23 M10Ks
Altera Arria II GX (C4) 1.4 Gbps 801 ALMs 12 to 19 M9Ks
Altera Arria II GZ (C3) 1.3 Gbps 818 ALMs 12 to 19 M9Ks
0 to 4 M144Ks
Altera Arria V GX (C4) 1.1 Gbps 714 ALMs 8 to 23 M10Ks
Altera Arria V GZ (C3) 1.4 Gbps 819 ALMs 4 to 36 M20Ks
Altera Stratix IV (C2) 1.4 Gbps 787 ALMs 12 to 19 M9Ks
0 to 4 M144Ks
Altera Stratix V (C2) 1.7 Gbps 831 ALMs 4 to 36 M20Ks
Lattice ECP3 (-8) 700 Mbps 1002 slices 4 to 12 EBRs
Microsemi AX (-1) 350 Mbps 2118 cells 19 to 50 RAMs
Microsemi ProASIC3L (-1) 280 Mbps 2873 tiles 19 to 25 RAMs
Xilinx Spartan-3A (-5) 600 Mbps 893 slices 4 to 12 RAMB16s
Xilinx Spartan-6 (-2) 800 Mbps 238 slices 4 to 20 RAMB16s
Xilinx Artix-7 (-2) 1.0 Gbps 226 slices 4 to 36 RAMB18s
Xilinx Virtex-5 (-3) 1.3 Gbps 221 slices 4 to 36 RAMB18s
Xilinx Virtex-6 (-3) 1.3 Gbps 225 slices 4 to 36 RAMB18s
Xilinx Virtex-7 (-2) 1.3 Gbps 228 slices 4 to 36 RAMB18s
Xilinx Kintex-7 (-2) 1.3 Gbps 227 slices 4 to 36 RAMB18s
Xilinx UltraSCALE (-2) 1.45 Gbps 172 CLBs 4 to 36 RAMB18s

1. Throughput figures are typical for the uncompressed interface and are data dependant.
2. These figures are for 2K history depth; the throughput will drop by up to 10%, and the area increase by up to 10% percent, for longer history depths and blocksizes.
3. RAM figures will vary with chosen history depth and blocksize. The range quoted covers history depths from 2K to a technology-dependent upper limit of 8K/16K/32K/64K (see datasheet for details). Greater depths would be possible with somewhat lower performance.

Datasheets

For full details of the Helion LZRW cores, please download the datasheet appropriate to your target technology.

Click here for the Altera FPGA core data sheet (PDF format)
Click here for the Xilinx FPGA core data sheet (PDF format)

Please contact Helion for availability in ASIC, Lattice and Microsemi (Actel) targets.

Contact

For more detailed information on this or any of our other products and services, please feel free to email us at helioncores@heliontech.com and we will be pleased to discuss how we can assist with your individual requirements.

 
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