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AES-XTS cores

Overview

The AES-XTS algorithm defined in NIST SP800-38E is in a class of algorithms known as "Tweakable" block ciphers, and is specified by the IEEE 1619 working group in their standard for disk encryption. In this application, AES-XTS is used to encrypt data at the disk sector level, where it addresses threats such as copy-and-paste attacks and dictionary attacks, while allowing the option of parallel processing for enhanced performance.

So why do we use AES-XTS?
When used for disk encryption, AES-XTS encrypts and decrypts blocks of 16-bytes at a time under the control of a secret AES key, and a "tweak" value derived from the logical position of the block on the disk. This algorithm fulfils the fundamental requirements for disk encryption, in that the data can be independently encrypted and decrypted at the sector level as it arrives in arbitrary order, and that the encryption process does not change the size of the data. In addition, the location of the data on the disk will vary the encrypted result, so that identical plaintext sectors stored at different places will not be the same after encryption.

Helion AES-XTS Solutions

Helion offer a suite of AES-XTS solutions which allow the user to choose a level of hardware acceleration which closely fits their requirement, minimising the amount of logic resources needed. Solutions are available that cover all data throughput levels from less than 1Gbps, to in excess of 64Gbps, in any of the target technologies supported.

Core type Typical Throughput Applications
Fast AES-XTS up to 3Gbps Single SATA 2.0 Hard disk
Twin Fast AES-XTS up to 6Gbps Single SATA 3.0 SSD
Giga AES-XTS up to 64Gbps Server Array

The table above shows the selection of standard AES-XTS solutions currently available from Helion. The baseline product is the Fast AES-XTS core, offering high data rates suitable for many applications. However, if you require more throughput, the Twin Fast AES-XTS core offers 2x the data rate of the Fast core, at less than twice the logic area. For even faster rates, the Giga AES-XTS core can be scaled as required, allowing the user to trade off logic area and performance to best match their application.

All Helion AES-XTS cores may be specified to support 128-bit and/or 256-bit key sizes, as well as optional Ciphertext Stealing - this allows sectors that are not an integer multiple of 16-bytes to be supported. We also have combined solutions which implement AES-XTS with other AES modes such as AES-ECB or AES-CBC, where multi protocol support is desired.

All of our high performance AES-XTS cores are available in versions for use in either ASIC, or Altera and Xilinx FPGA. In common with all Helion IP cores, they have been designed with each technology firmly in mind to yield the very best and most efficient results.

To find out how our AES-XTS solutions can be best utilised for your particular application, please contact Helion and we'll be happy to discuss the options open to you in more detail.

Measured Area and Performance
Fast AES-XTS
128-bit/256-bit key enc/dec version, without optional Ciphertext Stealing

TARGET TYPICAL THROUGHPUT AREA
ASIC (65nm CMOS) >3.2 Gbps <47k gates (TBC)
Altera Cyclone V (C6) >1.4 Gbps 3457 ALMs
Altera Arria II GX (C4) >1.8 Gbps 3785 ALMs
Altera Arria V GX (C4) >1.5 Gbps 3457 ALMs
Altera Arria V GZ (C3) >2.4 Gbps 3441 ALMs
Altera Arria 10 (E2L) >2.8 Gbps 3441 ALMs
Altera Stratix IV (C2) >2.3 Gbps 3777 ALMs
Altera Stratix V (C1) >2.8 Gbps 3419 ALMs
Xilinx Spartan-6 (-3) >1.1 Gbps 1375 slices
Xilinx Artix-7 (-3) >2.3 Gbps 1329 slices
Xilinx Virtex-6 (-3) >2.7 Gbps 1335 slices
Xilinx Kintex-7 (-3) >3.0 Gbps 1349 slices
Xilinx Virtex-7 (-3) >3.0 Gbps 1320 slices
Xilinx UltraSCALE (-2) >3.3 Gbps 729 CLBs


Twin Fast AES-XTS
128-bit/256-bit key enc/dec version, without optional Ciphertext Stealing

TARGET TYPICAL THROUGHPUT AREA
ASIC (65nm CMOS) >6.4 Gbps <81k gates (TBC)
Altera Cyclone V (C6) >2.9 Gbps 5570 ALMs
Altera Arria II GX (C4) >3.6 Gbps 6034 ALMs
Altera Arria V GX (C4) >2.9 Gbps 5547 ALMs
Altera Arria V GZ (C3) >4.7 Gbps 5524 ALMs
Altera Arria 10 (E2L) >5.5 Gbps 5565 ALMs
Altera Stratix IV (C2) >4.4 Gbps 5949 ALMs
Altera Stratix V (C1) >5.6 Gbps 5500 ALMs
Xilinx Spartan-6 (-3) >2.5 Gbps 1995 slices
Xilinx Artix-7 (-3) >4.6 Gbps 1877 slices
Xilinx Virtex-6 (-3) >5.4 Gbps 1921 slices
Xilinx Virtex-7 (-3) >6.3 Gbps 1938 slices
Xilinx Kintex-7 (-3) >6.3 Gbps 1950 slices
Xilinx UltraSCALE (-2) >6.9 Gbps 1140 CLBs

Remember that these are just two examples from a suite of AES-XTS solutions we have available, so if you are looking for even higher rate XTS cores, or maybe support for a target technology not shown, please contact Helion for full information.

Product Briefs

For full details of all the Helion AES-XTS cores, please download the appropriate Product Brief in PDF format below.

AES-XTS Cores - ASIC
AES-XTS Cores - FPGA

Contact

For more detailed information on this or any of our other products and services, please feel free to email us at helioncores@heliontech.com and we will be pleased to discuss how we can assist with your individual requirements.

Product Brief Quicklinks
AES-XTS Cores - ASIC
AES-XTS Cores - FPGA

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